Senior/Principal Researcher: Next-generation Computer Architecture for Racks and SuperPods

Huawei envisions a world where technology connects people, empowers industries, and unlocks human potential. Guided by its mission to enrich lives through communication and intelligent innovation, Huawei stands at the forefront of global digital transformation. As a leader in Information and Communications Technology (ICT), the company pioneers breakthroughs in artificial intelligence, cloud computing, and smart devices—building the intelligent foundation of a fully connected world.

Through its Carrier, Enterprise, and Consumer business groups, Huawei delivers resilient digital infrastructure, advanced cloud and AI platforms, and transformative devices that enable progress at every level. Supporting 45 of the world’s top 50 telecom operators and serving one-third of the global population across more than 170 countries, Huawei is shaping a future where connectivity becomes a powerful catalyst for opportunity and sustainable growth.

This spirit of bold innovation is embodied by Huawei Technologies Switzerland AG. From its research hubs in Zurich and Lausanne, pioneering teams push the boundaries of High-Performance Computing, Computer Architecture, Computer Vision, Robotics, Artificial Intelligence, Neuromorphic Computing, Wireless Technologies, and Networking—architecting the intelligent systems that will define tomorrow’s digital era.

Responsibilities:

• The research focuses on designing next-generation rack and SuperPod architectures that combine elasticity through resource pooling with optimal performance enabled by holistic co-design across applications, parallel programming models, interconnect fabrics, and compute, memory, and switch chip architectures. On the communication side, the work architects scalable, high-bandwidth, and low-latency scale-up fabrics across multiple chips at rack and SuperPod scale. On the memory side, it explores richer protocol semantics beyond traditional load/store operations to reduce unnecessary data movement and rethinks memory hierarchies to expose large-scale capacity with near-local latency. On the compute side, it analyzes the requirements of General Compute and Generative AI workloads and their parallel programming models to fully leverage large-scale system resources.
• Investigate and prototype new architectural features, including but not limited to:

- Tiered Memory: Explore advanced memory organizations, including hardware-managed caching, to enable software-transparent, fine-grained promotion and demotion of cache lines across the memory hierarchy.

- Prefetching/Speculation: Evaluate and design existing and next-generation hardware prefetching and speculation mechanisms to effectively hide local and remote memory latencies at rack and SuperPod scale.

- Near-Memory/Network Processing: Develop support for key primitives executed at the memory and network layers to minimize unnecessary data movement across sparse, dense, and pointer-based data structures.

- Workload-Centric Co-Design: Study optimal parallelization strategies at rack and SuperPod scale for both General Compute and Generative AI workloads, and design dedicated hardware support for widely used parallel programming primitives such as RPCs and collective communication.

• Produce and present research papers at top-tier conferences and journals (e.g., ASPLOS, ISCA, MICRO, HPCA)
• Establish and maintain collaborations with leading academic institutions and faculty.
• Mentor and support junior researchers and interns in their professional development.

Requirements:

• PhD in Computer Science, Electrical Engineering, or related field.
• Strong background in Computer Architecture and Computer Fabrics is a must.
• Creativity and the ability to think outside the box to develop innovative technologies.
• Research experience and/or strong knowledge in at least one of the following areas:

- Computer Architecture: Modern cache hierarchies, cache coherence protocols, memory systems, hardware prefetchers, and the memory-side of the core microarchitecture.

- Scale-up Fabrics: NVLink, UALink, CXL, UPI, IF, or PCIe.

- Parallel programming models: Collective libraires (NCCL or RCCL) and RPCs (gRPC or Thift).

- Workload optimization: General Compute and Generative AI workload composition (internals) and parallelization expertise at the scale of the rack or SuperPoD in both cloud and HPC environments.

• Proven track record of publishing research papers in top-tier conferences or journals.
• Excellent analytical, problem-solving, and system-level thinking skills.
• Strong interpersonal skills, with a collaborative spirit and the ability to work independently.

Why join us:

• Collaborate with world-class scientists and engineers in an open, curiosity-driven environment;
• Access to state-of-the-art technology and tools;
• Opportunities for professional growth and development;
• Competitive salary, and a high quality of life in Zurich, at the center of Europe;
• Last but certainly not least: be part of innovative projects that make a difference.