Veloce Emulation Application Engineer

Siemens seeks a mid-level Veloce Emulation Application Engineer in Bern to provide technical leadership, customer support, and deployment of hardware-assisted verification solutions.

This position delivers technical guidance and hands-on assistance to clients implementing Veloce hardware-assisted verification platforms. The engineer works closely with sales, R&D, and end-users to ensure successful emulation methodology adoption and resolve complex technical issues.

Responsibilities

• Offer technical assistance for Veloce emulation systems, covering initial setup, troubleshooting, and performance tuning.
• Assist clients with Virtual and ICE solution initialization, verifying low- and high-speed interface compliance with protocol standards and performance goals.
• Conduct technical sessions, product demos, and training for customers on Veloce emulation processes, tools, and best practices.
• Partner with marketing and research teams to convert client insights into product enhancements or new feature specifications.
• Monitor industry developments in emulation, verification approaches like UVM, and new technological advancements.

Requirements

• Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a closely related discipline.
• Minimum of five years of practical experience using hardware-assisted verification platforms, such as Veloce Strato, Palladium, ZeBu, or comparable systems.
• Familiarity with emulation acceleration, in-circuit emulation (ICE), and hybrid verification processes.
• Strong command of HDL languages including SystemVerilog and VHDL, along with HVL languages like C or SystemC.
• Fluent oral and written English communication skills.
• Customer-focused mindset paired with strong analytical problem-solving capabilities.

Nice to have

• Background in emulation off-load technology.
• Proficiency in scripting languages like Python or TCL.
• Practical experience verifying high-speed interfaces including PCIE 6.0, DDR5, Ethernet 400/800G, CXL 3.0, or UCIE 2.0.
• Knowledge of power analysis, low-power tools, DFT architecture, fault injection frameworks, coverage, and assertion methodologies.